Maury Wright, former editor-in-chief of EDN Magazine, has just posted a blog on the Intel embedded community site that provides an overview of QNX's bound multiprocessing technology — aka BMP.If you've never heard of BMP, it's a variant of symmetric multiprocessing (SMP) that simplifies the migration of legacy applications to multi-core processors. In a nutshell, it allows legacy apps to run on a multi-core chip as if they were still in a conventional uniprocessor environment. Meanwhile, it allows new, parallelized apps to take full advantage of the chip's multiple processing cores.
In other words, your old stuff can run on a multi-core chip without going haywire or messing up your new stuff. This is good.
Maury provides a nice overview of the technology. You can view his blog here.
5 comments:
I think SMP and its offshoot BMP are more of economic ideas than technical advantages. Better would be :
1. Single one-core processors with local memory which sit hot-plugged between whatever needs to be controlled and a Gbe backplane ( with PoE ).
2. Auxillary plug-in one-core processors with local memory for further graphics, A/D etc, also connected to the Gbe backplane.
3. One active one-core Supervisor Processor with local memory on the Gbe backplane.
The microkernel should be compiled for a single core with the higher apps providing distributed service. Failure of one processor or kernel will not effect the system.
The processor-memory can be a single module like the XPort RJ45 jack-computer from Lantronix. And the system can scale big. The machinery size will be much smaller than the usual multi-core multi-processor type.
Similar to the scene from the film 2001 : A Space Odyssey, when the ship computer HAL, is restarted by removing and re-plugging his processor? modules.
Sameer, your discrete processor approach would certainly enable greater reliability: by placing multiple cores on the same chip, we also create one large point of failure!
For more information about SMP, AMP, and BMP, see the Multicore Processing chapter of the QNX Neutrino System Architecture guide:
http://www.qnx.com/developers/docs/6.4.1/neutrino/sys_arch/smp.html
I highly think of SMP as a technical advantage. With separate CPUs, when one is 100% loaded and easily could use more power, and another CPU is idle, you can't do anything when the CPUs are separate. With SMP however, threads can easily migrate to a second CPU when the first one is too busy.
Of course, this approach does not scale beyond a certain number of CPUs, let's say 16. This is because the memory access is shared between all of them so this becomes the bottleneck.
@Steve Raid, I have gone through the link You provided. That document actually is not so much a 'Discrete vs SMP' talk as much a 'We also have SMP support' statement. I still remain un-SMP'ed.
Re : Malte's comment "With separate CPUs, when one is 100% loaded and easily could use more power, and another CPU is idle, you can't do anything when the CPUs are separate. With SMP however, threads can easily migrate to a second CPU when the first one is too busy".
With careful design and constrained design of both hardware and software, running apps paralelly or even Process Migration will not be burdensome.
I have never worked in the "industry" so I don't know the total applications-speed with SMP and with Discrete Processor systems. But I will say power considerations comes primarily in presence of display, fibre-optics, traditional and flash disks, USB, GPU, attached printers and scanners, and DRAM refresh. Maybe more in the list. Not much can be done about present technology but if they are immediately replaced t
Nantero's NRAM can be called Universal Memory. It is RAM but does not require refresh. It is also non-volatile memory so extra Flash Memory is not required. So immediately these power-consumptions are miniscule. As for Display, there are Projection techniques - those requiring a display-background and those who project holograms.
There is Ethernet which can interface every digital instrument (even only-memory modules ) replacing USB. Add to that, Power Over Ethernet and Power Line Communication, one has more power cut-backs.
Sorry have go leave now, but argument to be continued...
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